Time interleaved architecture allows the use of multiple identical analog-to-digital converters (ADCs) to process regular sample data series at a faster rate than the operating sample rate of each individual converter. It’s a good solution to implement high sampling rate converters at a moderate hardware cost. However, this concept suffers from mismatches between the ADC channels, such as offset, gain and timing skew. These mismatches have to be compensated in order to get sufficient performances from the converters.
Our ip is generic and built of correction and an estimation engin. It can estimate and correct those impairments for two interleaved converters.
With 2 parallel time multiplexed ADCs , one can double the sampling rate. So, for example, by interleaving 2 14-bit, 500 MSPS ADCs one could in principle realize a 14-bit, 1 GSPS ADC.
